Wafer Level Packaging Innovations

This cluster focuses on the technological advancements in wafer-level packaging (WLP). It reviews design and reliability issues, especially concerning electromigration in solder joints under various electrical stress conditions.

wafer-level packaging
electromigration
solder reliability
design issues
packaging advancements

358 papers

Parent topic: Advanced Electronic Packaging Technologies

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Papers Over Time

19751980198519901995200020052010201520202025

Top Papers

Design And Reliability In Wafer Level Packaging

2008 · 41 citations

Electromigration Of Pb-free Solder Under A Low Level Of Current Density

2008 · 36 citations

Electromigration In Flip Chip Solder Joints Under Extra High Current Density

2010 · 23 citations

Proceedings, 2008 International Conference On Electronic Packaging Technology & High Density Packaging (ICEPT-HDP 2008)

2008 · 14 citations

Wafer Level Chip Scale Packaging

2009 · 12 citations

High Power LED Packaging

2005 · 9 citations

Development Of Exposed Die Large Body To Die Size Ratio Wafer Level Package Technology

2014 · 8 citations

High Density Microwave Packaging Program

0 · 6 citations

Packaging Technology For Imager Using Through-Hole Interconnections In Si Substrate

0 · 5 citations

Packaging Effect On Reliability Of Cu/low K Interconnects

0 · 5 citations

Microelectronics Packaging Processing Using Focused High Power Electron Beams

0 · 5 citations

High Density Interconnect Processes For Panel Level Packaging

2018 · 5 citations

Summary Abstract: Interfacial Roughness In High Frequency Microelectronic Interconnections And Packaging

1985 · 4 citations

Assessment Of Au Stud-Solder Interconnection For Fine Pitch Flip Chip Packaging

2007 · 3 citations

High Performance Integrated Circuit Packaging

0 · 2 citations

Wafer Level Chip Scale Packaging

2016 · 2 citations

Reliability Predictions For High Density Packaging

0 · 2 citations

Effect Of Current Density And Geometry Structure On Pb-free Solder Joints Electromigration

0 · 2 citations

A Low Cost Wafer Level Packaging Process

0 · 2 citations

Micro-Interconnection(Japan Institute Of Electronics Packaging)

2013 · 1 citations