Circuit Design Performance Optimization

This cluster focuses on performance optimization techniques specifically for VLSI circuits. It emphasizes yield and speed enhancement strategies in circuit design.

circuit design
performance optimization
yield
speed enhancement
techniques
VLSI

2,888 papers

Parent topic: VLSI Design and Technologies

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Papers Over Time

197019801990200020102020

Top Papers

Yield And Speed Optimization Of A Latch-Type Voltage Sense Amplifier

2004 · 375 citations

A 32 Kb 10T Sub-Threshold SRAM Array With Bit-Interleaving And Differential Read Scheme In 90 Nm CMOS

2009 · 358 citations

Stacked Inductors And Transformers In CMOS Technology

2001 · 273 citations

Coplanar Full Adder In Quantum-Dot Cellular Automata Via Clock-Zone-Based Crossover

2015 · 192 citations

Design And Optimization Of Multithreshold Cmos (Mtcmos) Circuits

2003 · 130 citations

A 16-Bit Low-Voltage CMOS A/D Converter

1987 · 122 citations

A 200 MHz 13 Mm/Sup 2/ 2-D DCT Macrocell Using Sense-Amplifying Pipeline Flip-Flop Scheme

1994 · 113 citations

TSV Redundancy: Architecture And Design Issues In 3-D IC

2012 · 110 citations

Transistor Sizing Issues And Tool For Multi-threshold Cmos Technology

0 · 102 citations

A High-Performance 0.25- Mu M CMOS Technology. II. Technology

1992 · 96 citations

A Cost-Efficient High-Performance Dynamic TCAM With Pipelined Hierarchical Searching And Shift Redundancy Architecture

2005 · 87 citations

Self-aligned Bipolar Transistors For High-Performance And Low-Power-Delay VLSI

1981 · 80 citations

Measurements And Analysis Of SER-tolerant Latch In A 90-Nm dual-V/sub T/ CMOS Process

2004 · 71 citations

Z-TCAM: An SRAM-based Architecture For TCAM

2015 · 66 citations

A double-level-V/sub Th/ Select Gate Array Architecture For Multilevel NAND Flash Memories

1996 · 66 citations

Incorporation Of Metal Silicides And Refractory Metals In VLSI Technology

1991 · 63 citations

Design And Iso-Area $V_{\min}$ Analysis Of 9T Subthreshold SRAM With Bit-Interleaving Scheme In 65-Nm CMOS

2012 · 60 citations

A 13.3-Mb/s 0.35-Μm CMOS Analog Turbo Decoder IC With A Configurable Interleaver

2003 · 58 citations

1Gbit High Density Embedded STT-MRAM In 28Nm FDSOI Technology

2019 · 58 citations

Complementary-LVTSCR ESD Protection Circuit For Submicron CMOS VLSI/ULSI

1996 · 56 citations