Low-Power CMOS Design Techniques

This cluster studies design approaches for creating low-power CMOS integrated circuits. It focuses on strategies to minimize power consumption and address leakage current issues.

low-power

CMOS

design techniques

leakage current

optimization

power consumption

11,978 papers

Parent topic: VLSI Design and Technologies

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Papers Over Time

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Top Papers

Low-power CMOS Digital Design

1992 · 1,883 citations

Leakage Current Mechanisms And Leakage Reduction Techniques In Deep-Submicrometer CMOS Circuits

2003 · 1,679 citations

On-chip High-Voltage Generation In MNOS Integrated Circuits Using An Improved Voltage Multiplier Technique

1976 · 1,334 citations

A Regular Layout For Parallel Adders

1982 · 734 citations

A 1.5-V, 10-Bit, 14.3-MS/s CMOS Pipeline Analog-To-Digital Converter

1999 · 719 citations

Extracting Secret Keys From Integrated Circuits

2005 · 639 citations

2010 · 635 citations

CMOS Analog Integrated Circuits Based On Weak Inversion Operations

1977 · 623 citations

Low Power Digital CMOS Design

1995 · 607 citations

High-speed CMOS Circuit Technique

1989 · 599 citations

Combinatorial Algorithms For Integrated Circuit Layout

1990 · 471 citations

Trends And Challenges In VLSI Circuit Reliability

2003 · 461 citations

Fundamentals Of Modern VLSI Devices

2009 · 440 citations

Device Mismatch And Tradeoffs In The Design Of Analog Circuits

2005 · 363 citations

High-speed Compact Circuits With CMOS

1982 · 360 citations

Cascode Voltage Switch Logic: A Differential CMOS Logic Family

1984 · 348 citations

A 3.8-Ns CMOS 16*16-B Multiplier Using Complementary Pass-Transistor Logic

1990 · 346 citations

Performance Analysis Of Low-Power 1-Bit CMOS Full Adder Cells

2002 · 339 citations

CORDIC-based VLSI Architectures For Digital Signal Processing

1992 · 336 citations

CMOS Circuit Speed And Buffer Optimization

1987 · 335 citations