CMOS Innovations for Communication

Focusing on the application of CMOS circuits in communication technologies, this cluster explores circuit designs tailored for high-speed and efficient data transmission. Research spans various communication protocols and standards.

CMOS
Communication
High-Speed
Data Transmission
Circuit Design

1,724 papers

Parent topic: CMOS and High-Frequency Circuit Design

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Papers Over Time

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Top Papers

1.25-Gb/s Regulated Cascode CMOS Transimpedance Amplifier For Gigabit Ethernet Applications

2004 · 264 citations

22Nm FDSOI Technology For Emerging Mobile, Internet-of-Things, And RF Applications

2016 · 199 citations

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver In 90-Nm CMOS Technology

2006 · 170 citations

A 480 mW 2.6 GS/s 10B Time-Interleaved ADC With 48.5 dB SNDR Up To Nyquist In 65 Nm CMOS

2011 · 106 citations

OC-192 Transmitter And Receiver In Standard 0.18-Μm CMOS

2002 · 95 citations

Analog Integrated Circuits For Communication

1991 · 93 citations

A 2-V CMOS Cellular Transceiver Front-End

2000 · 84 citations

A Fully Integrated spiral-LC CMOS VCO Set With Prescaler For GSM And DCS-1800 Systems

0 · 72 citations

A 0.8-Μm CMOS 2.5 Gb/s Oversampling Receiver And Transmitter For Serial Links

1996 · 68 citations

A Fully Integrated CMOS Frequency Synthesizer With Charge-Averaging Charge Pump And Dual-Path Loop Filter For PCS- And cellular-CDMA Wireless Systems

2002 · 66 citations

A Quad-Core 15GHz BiCMOS VCO With −124dBc/Hz Phase Noise At 1MHz Offset, −189dBc/Hz FOM, And Robust To Multimode Concurrent Oscillations

2018 · 57 citations

LC-VCO Design Optimization Methodology Based On The $g_m/I_D$ Ratio For Nanometer CMOS Technologies

2011 · 46 citations

0.25-<Inline-Formula> <Tex-Math notation="LaTeX">$\mu \Text{M}$ </Tex-Math> </Inline-Formula> BiCMOS System-on-Chip For K-/Ka-Band Satellite Communication Transmit–Receive Active Phased Arrays

2018 · 46 citations

9.5 A Dual-Band digital-WiFi 802.11A/B/G/N Transmitter SoC With Digital I/Q Combining And Diamond Profile Mapping For Compact Die Area And Improved Efficiency In 40Nm CMOS

2016 · 44 citations

A 112 Gb/s PAM4 Linear TIA With 0.96 pJ/bit Energy Efficiency In 28 Nm CMOS

2018 · 43 citations

Ultra-wide Body-Bias Range LDPC Decoder In 28Nm UTBB FDSOI Technology

2013 · 42 citations

CMOS Power Amplifier Integrated Circuit With Dual-Mode Supply Modulator For Mobile Terminals

2016 · 40 citations

A Low-Power CMOS Chipset For Spread Spectrum Communications

0 · 39 citations

Digital Adaptive IIP2 Calibration Scheme For CMOS Downconversion Mixers

2008 · 38 citations

Adaptive Multi-Standard Circuits And Systems For Wireless Communications

2006 · 37 citations